WM8720

Production Data

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PD Rev 4.0 February 2005

14

DAC OUTPUT CONTROL

Bits 5, 6, 7 and 8 (PL[3:0]) of register 2 are used to control the output format as shown in Table 11.

PL3

PL2

PL1

PL0

LEFT

OUTPUT

RIGHT

OUTPUT

NOTE

0

0

0

0

MUTE

MUTE

Mute both channels

0

0

0

1

L

MUTE

0

0

1

0

R

MUTE

0

0

1

1

(L + R)/2

MUTE

0

1

0

0

MUTE

L

0

1

0

1

L

L

0

1

1

0

R

L

Reverse channels

0

1

1

1

(L + R)/2

L

1

0

0

0

MUTE

R

1

0

0

1

L

R

Stereo mode

1

0

1

0

R

R

1

0

1

1

(L + R)/2

R

1

1

0

0

MUTE

(L + R)/2

1

1

0

1

L

(L + R)/2

1

1

1

0

R

(L + R)/2

1

1

1

1

(L + R)/2

(L + R)/2

Mono mode

Table 11 Programmable DAC Output Format

SERIAL PROTOCOL

Bits 0 (I

bit 0 (I

(I

POLARITY OF LRCIN SELECT

Bit 1 (LRP) of register 3 is used to control the polarity of LRCIN (sample rate clock). When bit 1 is

low (LRP = 0), left channel data is assumed when LRCIN is in a high phase and right channel data

is assumed when LRCIN is in a low phase. When bit 1 is high (LRP = 1), the polarity assumption

is reversed.

INTERFACE CLOCKS AND SAMPLING RATES

Bits 6 (SF0) and 7 (SF1) of register 3 are used to control the sampling frequency, as shown in

Table 12.

SF0

SF1

SAMPLING FREQUENCY

0

0

44.1 kHz group

22.05 / 44.1 / 88.2 kHz

0

1

48 kHz group

24 / 48 / 96 kHz

1

0

32 kHz group

16 / 32 / 64 kHz

1

1

Reserved

Not defined

Table 12 Sampling Frequencies

INFINITE ZERO DETECTION

Bit 8 (IZD) in register 3 controls operation of the automute function. If IZD (Infinite Zero Detect) is

high, 1024 consecutive zero audio samples will force the output to zero. See Figure 6. Note that the

control of pin MUTE also affects automute operation. To turn off automute, pin MUTE must be held

low as well as IZD being low (default).