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AT89C5131A-RDTIM 数据表(PDF) 98 Page - ATMEL Corporation |
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AT89C5131A-RDTIM 数据表(HTML) 98 Page - ATMEL Corporation |
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98 / 186 page  98 AT89C5130A/31A-M 4337G–USB–11/06 Reset Value = 0001 0100b Not bit addressable Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write collision • Inconsistent logic level on SS pin (mode fault error) Table 75 describes the SPSTA register and explains the use of every bit in the register. Table 75. SPSTA Register SPSTA - Serial Peripheral Status and Control register (0C4H) 1SPR1 SPR2 SPR1 SPR0 Serial Peripheral Rate 0 0 0 Reserved 00 1 FCLK PERIPH/4 01 0 FCLK PERIPH/8 01 1 FCLK PERIPH/16 10 0 FCLK PERIPH/32 10 1 FCLK PERIPH/64 11 0 FCLK PERIPH/128 1 1 1 Reserved 0SPR0 Bit Number Bit Mnemonic Description 7654 3210 SPIF WCOL SSERR MODF - - - - Bit Number Bit Mnemonic Description 7SPIF Serial Peripheral data transfer flag Cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. 6WCOL Write Collision flag Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. 5SSERR Synchronous Serial Slave Error flag Set by hardware when SS is de- asserted before the end of a received data. Cleared by disabling the SPI (clearing SPEN bit in SPCON). 4MODF Mode Fault Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level. 3- Reserved The value read from this bit is indeterminate. Do not set this bit |
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