AT89C5131A-RDTIM datasheet(129/186 Pages) ATMEL

129 / 186 page

129

AT89C5130A/31A-M

4337G–USB–11/06

If the Host sends more bytes than supported by the endpoint FIFO, the overflow data

won’t be stored, but the USB controller will consider that the packet is valid if the CRC is

correct.

Isochronous IN Transactions

in Standard Mode

An endpoint will be first enabled and configured before being able to send Isochronous

packets.

The firmware will fill the FIFO with the data to be sent and set the TXRDY bit in the UEP-

STAX register to allow the USB controller to send the data stored in FIFO at the next IN

request concerning this endpoint.

If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB

controller.

When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by

the USB controller. This triggers a USB interrupt if enabled. The firmware will clear the

TXCMPL bit before filling the endpoint FIFO with new data.

The firmware will never write more bytes than supported by the endpoint FIFO

Isochronous IN Transactions

in Ping-pong Mode

An endpoint will be first enabled and configured before being able to send Isochronous

packets.

The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in

the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the

next IN request concerning the endpoint. The FIFO banks are automatically switched,

and the firmware can immediately write into the endpoint FIFO bank 1.

If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB

controller.

When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the

USB controller. This triggers a USB interrupt if enabled. The firmware will clear the TXC-

MPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then

automatically switched.

When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the

USB controller. This triggers a USB interrupt if enabled. The firmware will clear the TXC-

MPL bit before filling the endpoint FIFO bank 1 with new data.

The bank switch is performed by the USB controller each time the TXRDY bit is set by

the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,

the USB controller won’t send anything at each IN requests concerning this bank.

The firmware will never write more bytes than supported by the endpoint FIFO.

AT89C5131A-RDTIM 数据表(PDF) 129 Page - ATMEL Corporation

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