ADCMP580/ADCMP581/ADCMP582

Rev. 0 | Page 10 of 16

TYPICAL APPLICATION CIRCUITS

Q

ADCMP580

Q

LATCH

INPUTS

50

Ω

50

Ω

GND

Figure 17. Zero-Crossing Detector with CML Outputs

Q

ADCMP581

Q

LATCH

INPUTS

50

Ω

50

Ω

Figure 18. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver

HYS

50

Ω

50

Ω

ADCMP580

0

Ω TO 5kΩ

Figure 19. Adding Hysteresis Using the HYS Control

50

Ω

50

Ω

+

–

Q

Q

LATCH

INPUTS

GND

ADCMP580

Figure 20. Comparator with −2 to +3 V Input Range

ADCMP580

50

Ω

1.5k

Ω

50

Ω

CML

Figure 21. Disabling the Latch Feature on the ADCMP580

ADCMP581

50

Ω

50

Ω

450

Ω

RSECL

Figure 22. Disabling the Latch Feature on the ADCMP581

ADCMP582

50

Ω

1k

Ω

50

Ω

RSPECL

Figure 23. Disabling the Latch Feature on the ADCMP582