ADCMP580/ADCMP581/ADCMP582

Rev. 0 | Page 12 of 16

OPTIMIZING HIGH SPEED PERFORMANCE

As with any high speed comparator, proper design and layout

techniques are essential to obtaining the specified performance.

Stray capacitance, inductance, inductive power, and ground

impedances or other layout issues can severely limit performance

and can cause oscillation. Discontinuities along input and output

transmission lines can also severely limit the specified pulse

width dispersion performance.

For applications in a 50 Ω environment, input and output

matching have a significant impact on data-dependent (or

deterministic) jitter (DJ) and pulse width dispersion

performance. The ADCMP58x family of comparators provides

The return side for each termination is pinned out separately

pins can be connected (or disconnected) to (from) the desired

termination potential as appropriate. The termination potential

should be carefully bypassed using ceramic capacitors as dis-

cussed previously to prevent undesired aberrations on the input

signal due to parasitic inductance in the termination return

path. If a 50 Ω termination is not desired, either one or both

case, the open pins should be left floating with no external pull

downs or bypassing capacitors.

For applications that require high speed operation but do not

have on-chip 50 Ω termination resistors, some reflections

should be expected, because the comparator inputs can no

longer provide matched impedance to the input trace leading

up to the device. It then becomes important to back-match the

drive source impedance to the input transmission path leading

to the input to minimize multiple reflections. For applications

in which the comparator is less than 1 cm from the driving

signal source, the source impedance should be minimized. High

source impedance in combination with parasitic input capaci-

tance of the comparator could cause undesirable degradation

in bandwidth at the input, thus degrading the overall response.

It is therefore recommended that the drive source impedance

should be no more than 50 Ω for best high speed performance.

COMPARATOR PROPAGATION

DELAY DISPERSION

The ADCMP58x family of comparators has been specifically

designed to reduce propagation delay dispersion over a wide

input overdrive range of 5 mV to 500 mV. Propagation delay

dispersion is a change in propagation delays, which results

from a change in the degree of overdrive or slew rate (how far

or fast the input signal exceeds the switching threshold). The

overall result is a higher degree of timing accuracy.

Propagation delay dispersion is a specification that becomes

important in critical timing applications, such as data commu-

nication, automatic test and measurement, instrumentation,

and event-driven applications, such as pulse spectroscopy,

nuclear instrumentation, and medical imaging. Dispersion

is defined as the variation in the overall propagation delay as

the input overdrive conditions are changed (see Figure 26 and

Figure 27). For the ADCMP58x family of comparators, disper-

sion is typically <25 ps, as the overdrive varies from 5 mV to

500 mV, and the input slew rate varies from 1 V/ns to 10 V/ns.

This specification applies for both positive and negative signals,

because the ADCMP58x family of comparators has almost

equal delays for positive- and negative-going inputs.

Q/Q OUTPUT

INPUT VOLTAGE

500mV OVERDRIVE

5mV OVERDRIVE

DISPERSION

Figure 26. Propagation Delay—Overdrive Dispersion

Q/Q OUTPUT

INPUT VOLTAGE

10V/ns

1V/ns

DISPERSION

Figure 27. Propagation Delay—Slew Rate Dispersion