USB97C102 datasheet(27/80 Pages) SMSC

27 / 80 page

SMSC DS – USB97C102

Page 27

Rev. 03/23/2000

Table 30 - FLASH Bank Select Register 2

MEM_BANK2

(0x7F28 - RESET=0x00)

FLASH BANK SELECT REGISTER 2

BIT

NAME

R/W

DESCRIPTION

[7:6]

Reserved

[5:0]

A[19:14]

R/W

This register selects which 16k page resides at 0x8000-0xBFFF in

Code Space and 0x8000-0xBFFF in Data Space.

Table 31 - FLASH Bank Select Register

MEM_BANK

(0x7F29 - RESET=0x01)

FLASH BANK SELECT REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:6]

Reserved

[5:0]

A[19:14]

R/W

This register selects which 16k page resides at 0x4000-0x7FFF in

Code Space and 0xC000-0xFFFF in Data Space. The 0x0000-

0x3FFF page will always reflect the 16K FLASH page 0 (0x00000-

0x03FFF).

Table 32 - Wakeup Source 1 Register

WU_SRC_1

(0x7F2A – RESET=0x00)

WAKEUP SOURCE 1

BIT

NAME

R/W

DESCRIPTION

[7:3]

Reserved

R/W

Reserved

USB_Reset

R/W

This bit is set when the SIE detects simultaneous logic lows on D+

and D- (Single-Ended 0) for 32 to 64 full speed bit times, or 4 to 8 low

speed bit times (or 2.5<t<5.5us). The USB_Reset signal may be as

long as 10ms. SETUP tokens can be NAK'd for up to 10ms after the

Reset signal is released.

Resume

R/W

This bit is set on detection of Global Resume state (when there is a

transition from the "J" state while in Global Suspend).

Suspend

R/W

Suspend – If 3ms of IDLE state are detected by the hardware, then

this bit will be set.

Note 1: Only low to high transitions for the associated inputs sets these bits.

Note 2: The bits in this register are cleared by writing a ‘1’ to the corresponding bit.

Note 3: Unmasked Wakeup Source bits generate an INT1 PWR_MNG interrupt, and restart the 8051 when its clock

is stopped. This restarts the Ring Oscillator and crystal oscillator for the MCU to resume from <500µA

operation.

Note 4: To initiate USB Remote Wakeup, the SIE_Resume bit should be used in the SIE_CONFIG register.

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