USB97C102 datasheet(39/80 Pages) SMSC

39 / 80 page

SMSC DS – USB97C102

Page 39

Rev. 03/23/2000

The SGDMA also contains a PIO engine that permits the MCU to access the ISA bus on a cycle stealing basis with

the DMA transfers (there is only one PIO engine).

Table 62 – SGDMA Packet Number Start FIFO Register

SGDMA_START_FIFOx [x=0..3]

(BASE+0 – RESET = 0x00)

SGDMA_START_FIFO

BIT

NAME

R/W

DESCRIPTION

[7:5]

Reserved

R/W

Reserved – Read back as 0

[4:0]

PCKTNUM

R/W

Packet Number to queue on

SGDMA_START_FIFOx [x=0..3].

Note 1: This register is used when the channel is configured for an MMU memory operation.

Note 2: When the channel is enabled (CHANNEL_ENABLE=1 in register SGDMA_CMDx [x=0..3]), only the SGDMA

can read from these registers. The MCU can only read from these registers when the channel is disabled

(CHANNEL_ENABLE=0 in register SGDMA_CMDx [x=0..3]), and not busy (DMA_BUSY=0 in register

SGDMA_STSx [x=0..3]). It is the MCU’s responsibility to ensure that this FIFO does not overflow.

Table 63 – SGDMA Packet Number Done FIFO Register

SGDMA_DONE_FIFOx [x=0..3]

(BASE+1 – RESET = 0x00)

SGDMA_DONE_FIFO

BIT

NAME

R/W

DESCRIPTION

[7:5]

Reserved

R/W

Reserved – Read back as 0.

[4:0]

PCKTNO

R/W

Packet Number on top of the

SGDMA_DONE_FIFOx [x=0..3].

Note 1: This register is used when the channel is configured for an MMU memory operation.

Note 2: The SGDMA puts the packet number on this FIFO when the DMA transfer is complete, or when the MCU

disables a channel that was enabled and busy (meaning a DMA transfer was in progress). When this

overflow.

Table 64 – SGDMA ISA Address High Byte Register

SGDMA_ADHIx [x=0..3]

(BASE+2 – RESET = 0x00)

SGDMA_ADHI

BIT

NAME

R/W

DESCRIPTION

[7:0]

ADHIx [x=0..3]

R/W

Contains the high byte of the ISA

Address to use.

Table 65 – SGDMA ISA Address Low Byte Register

SGDMA_ADLOx [x=0..3]

(BASE+3 – RESET = 0x00)

SGDMA_ADLO

BIT

NAME

R/W

DESCRIPTION

[7:0]

ADLOx [x=0..3]

R/W

Contains the low byte of the ISA Address

to use.

Note 1: The SGDMA_ADHIx [x=0..3] and SGDMA_ADLOx [x=0..3] registers are used when the channel [0..3] is

configured for an ISA memory operation.

Note 2: The MCU must not write to these registers unless the channel is disabled (CHANNEL_ENABLED=0 in

Table 66 – SGDMA Transfer Size High Register

SGDMA_SIZEHIx [x=0..3]

(BASE+4 – RESET = 0x00)

SGDMA_SIZEHI

BIT

NAME

R/W

DESCRIPTION

[7:0]

SIZEHIx

[x=0..3]

R/W

Contains the high byte of the payload

data size (in bytes)

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