AM29PL320DB70RWPI datasheet(24/49 Pages) AMD

24 / 49 page

Am29PL320D

June 13, 2005

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 13

shows the address and data requirements for the chip

erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. The Chip Erase

command sequence should be reinitiated once the

device has returned to reading array data, to ensure

data integrity.

The system can determine the status of the erase op-

eration by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the Program/Erase Operations tables in “AC

Characteristics” for parameters, and to Figure 18 for

timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 13 shows the address and data

requirements for the sector erase command sequence.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector

for an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The in-

terrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase Sus-

pend during the time-out period resets the device

to reading array data. The system must rewrite the

command sequence and any additional sector ad-

dresses and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, or DQ2.

(Refer to “Write Operation Status” for information on

these status bits.)

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Program/Erase Operations tables in

the “AC Characteristics” section for parameters, and to

Figure 18 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase

Suspend command.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maxi-

mum of 20 µs to su spend the erase operation.

However, when the Erase Suspend command is writ-

ten during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

AM29PL320DB70RWPI 数据表(PDF) 24 Page - Advanced Micro Devices

AM29PL320DB70RWPI 数据表(HTML) 24 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

数据表下载