AM29PDL128G datasheet(13/71 Pages) AMD

13 / 71 page

Am29PDL128G

October 28, 2004

P R E L IM IN A R Y

inputs (assuming the addresses have been stable for

at least t

ACC–tOE time).

Page Mode Read

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. The page size of

the device is 8 words, or 4 double words, with the ap-

propriate page being selected by the higher address

bits A21–A2 and the LSB bits A1–A0 (in the double

word mode) and A1 to A-1 (in the word mode) deter-

mining the specific word/double word within that page.

This is an asynchronous operation with the micropro-

cessor supplying the specific word or double word lo-

cation.

The random or initial page access is equal to t

ACC or

CE and subsequent page read accesses (as long as

the locations specified by the microprocessor falls

within that page) is equivalent to t

PACC. When CE# is

deasserted and reasserted for a subsequent access,

the access time is t

ACC or tCE. Here again, CE# selects

the device and OE# is the output control and should

be used to gate data to the output inputs if the device

is selected. Fast page mode accesses are obtained by

keeping A21–A2 constant and changing A1 to A0 to

select the specific double word, or changing A1 to A-1

to select the specific word, within that page.

Table 2.

Page Select, Double Word Mode

Table 3.

Page Select, Word Mode

Simultaneous Operation

The device is capable of reading data from one bank

of memory while a program or erase operation is in

progress in another bank of memory (simultaneous

operation), in addition to the conventional features

(read, program, erase-suspend read, and erase-sus-

pend program). The bank selected can be selected by

bank addresses (A21–A19) with zero latency.

The simultaneous operation can execute multi-func-

tion mode in the same bank.

Table 4.

Bank Select

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

IL, and OE# to VIH.

For program operations, the WORD# pin determines

whether the device accepts program data in double

words or words. Refer to “Word/Double Word Configu-

ration” for more information.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a double word or word, instead of four. See

“Double Word/Word Program Command Sequence”

on page 36 for details on programming data to the de-

vice using both standard and Unlock Bypass com-

mand sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 5 indicates the address

space that each sector occupies. A “bank address” is

the address bits required to uniquely select a bank.

Similarly, a “sector address” refers to the address bits

required to uniquely select a sector. The “Command

Definitions” section has details on erasing a sector or

the entire chip, or suspending/resuming the erase op-

eration.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. See “AC

Characteristics” on page 53 for timing specification ta-

bles and timing diagrams for write operations.

Word

Double Word 0

Double Word 1

Double Word 2

Double Word 3

Word

A-1

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

Bank

A21–A19

Bank 1

000

Bank 2

001, 010, 011

Bank 3

100, 101, 110

Bank 4

111

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