BS640HD8V datasheet(65/89 Pages) AMD

65 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

AC CHARACTERISTICS

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) RDY goes low during the two-cycle latency during a boundary crossing.

2) RDY stays high when a burst sequence crosses no boundaries.

Figure 25.

Standard Handshake Burst Suspend Prior to Initial Access

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Burst suspend during the initial synchronous access

2) Burst suspend after one clock cycle following the initial synchronous access

Figure 26.

Standard Handshake Burst Suspend at or after Initial Access

Addresses

A(n)

AVD#

Data(2)

RDY(2)

RDY(1)

tOES

tCKA

tRACC

x+1

x+2

x+3

x+4

x+5

x+6

x+7

x+8

OE#

Data(1)

tACC

D(40)

D(3F)

D(n)

D(n+1)

D(n+2)

CLK

D(n)

D(n+1)

D(n+2)

D(n+3)

D(n+4)

D(n+5)

D(n+6)

Suspend

Resume

Addresses

A(n)

AVD#

OE#(1)

Data(1)

Data(2)

OE#(2)

RDY(1)

D(n)

D(n+1)

Suspend

Resume

ACC

tRACC

OES

CKA

D(n)

OES

x+1

x+2

x+3

CLK

RACC

OES

RACC

CKA

D(n+1)

D(n+2)

D(n)

D(n+1)

tRACC

CKZ

RDY(2)

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