BS640HD8V datasheet(79/89 Pages) AMD

部件名	BS640HD8V

功能描述	128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

PDF	89 Pages

Scroll/Zoom	100%

制造商	AMD [Advanced Micro Devices]

网页	http://www.amd.com

标志

79 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

AC CHARACTERISTICS

Notes:

1. The timings are similar to synchronous read timings.

2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the

toggle bits will stop toggling.

3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one

clock cycle before data.

Figure 42.

Synchronous Data Polling Timings/Toggle Bit Timings

CE#

CLK

AVD#

Addresses

OE#

Data

RDY

Status Data

tIACC

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 43.

DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read

Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

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