BS640HD8V datasheet(67/89 Pages) AMD

67 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

AC CHARACTERISTICS

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Address is 3Eh or offset by a multiple of 64 (40h)

2) Address is 3Fh or offset by a multiple of 64 (40h)

Figure 29.

Standard Handshake Burst Suspend at Address 3Eh/3Fh (with 1 Access CLK)

Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence

has been written with A18=0; device will output RDY with valid data.

1) Device crosses a page boundary prior to tRCC.

2) Device neither crosses a page boundary nor latches a new address prior to tRCC.

Figure 30.

Read Cycle for Continuous Suspend

Addresses(1)

A(3E)

AVD#

CLK

x+1

x+2

x+3

x+4

x+5

x+6

OE#

Data(1)

Addresses(2)

Data(2)

RDY(2)

(Odd)

RDY(1)

(Even)

D(3E)

D(3F)

D(41)

D(40)

D(42)

D(40)

D(42)

D(41)

D(43)

Suspend

Resume

OES

tACC

tRACC

tCKZ

tOES

tCKA

A(3F)

D(3F)

tRACC

D(40)

tRACC

Addresses

A(n)

AVD#

Data(2)

CE#

RDY

D(n)

???

tOES

tCKA

tRACC

tRCC

???

x+1

x+2

x+3

x+4

x+5

x+6

x+7

x+8

OE#

Data(1)

tACC

D(40)

D(3F)

D(n)

D(n+1)

D(n+2)

D(3F)

CLK

Suspend

Resume

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