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PCF85063ATT/AJ 数据表(PDF) 5 Page - NXP Semiconductors |
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PCF85063ATT/AJ 数据表(HTML) 5 Page - NXP Semiconductors |
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5 / 55 page ![]() NXP Semiconductors PCF85063A Tiny Real-Time Clock/calendar with alarm function and I2C-bus 7.1 Registers organization Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 7. Bit Address Register name 7 6 5 4 3 2 1 0 Reference Control and status registers 00h Control_1 EXT_TEST - STOP SR - CIE 12_24 CAP_SEL Section 7.2.1 01h Control_2 AIE AF MI HMI TF COF[2:0] Section 7.2.2 02h Offset MODE OFFSET[6:0] Section 7.2.3 03h RAM_byte B[7:0] Section 7.2.4 Time and date registers 04h Seconds OS SECONDS (0 to 59) Section 7.3.1 05h Minutes - MINUTES (0 to 59) Section 7.3.2 AMPM HOURS (1 to 12) in 12-hour mode 06h Hours - - HOURS (0 to 23) in 24-hour mode Section 7.3.3 07h Days - - DAYS (1 to 31) Section 7.3.4 08h Weekdays - - - - - WEEKDAYS (0 to 6) Section 7.3.5 09h Months - - - MONTHS (1 to 12) Section 7.3.6 0Ah Years YEARS (0 to 99) Section 7.3.7 Alarm registers 0Bh Second_alarm AEN_S SECOND_ALARM (0 to 59) Section 7.5.1 0Ch Minute_alarm AEN_M MINUTE_ALARM (0 to 59) Section 7.5.2 AMPM HOUR_ALARM (1 to 12) in 12-hour mode 0Dh Hour_alarm AEN_H - HOUR_ALARM (0 to 23) in 24-hour mode Section 7.5.3 0Eh Day_alarm AEN_D - DAY_ALARM (1 to 31) Section 7.5.4 0Fh Weekday_alarm AEN_W - - - - WEEKDAY_ALARM (0 to 6) Section 7.5.5 Timer registers 10h Timer_value T[7:0] Section 7.6.1 11h Timer_mode - - - TCF[1:0] TE TIE TI_TP Section 7.6.2 Table 4. Registers overview 7.2 Control registers To ensure that all control registers will be set to their default values, the VDD level must be at zero volts at initial power-up. If this is not possible, a reset must be initiated with the software reset command when power is stable. Refer to Section 7.2.1.3 for details. 7.2.1 Register Control_1 Bit Symbol Value Description Reference external clock test mode 0[1] normal mode 7 EXT_TEST 1 external clock test mode Section 7.2.1.1 6 - 0 unused - STOP bit 5 STOP 0[1] RTC clock runs Section 7.2.1.2 Table 5. Control_1 - control and status register 1 (address 00h) bit description PCF85063A All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 7.1 — 8 November 2023 5 / 55 |
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