LTM4680 datasheet(13/36 Pages) AD

13 / 36 page

LTM4650-2

Rev. 0

For more information www.analog.com

Figure 5. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table

46502 F05

VOUT2

180-PHASE

0-PHASE

MODE_PLLIN

VOUT1

PHASMD

CLKOUT

2-PHASE DESIGN

4-PHASE DESIGN

6-PHASE DESIGN

90-DEGREE

FLOAT

VOUT2

180-PHASE

0-PHASE

FLOAT

MODE_PLLIN

VOUT1

PHASMD

CLKOUT

VOUT2

270-PHASE

90-PHASE

FLOAT

MODE_PLLIN

VOUT1

PHASMD

CLKOUT

60-DEGREE

VOUT2

180-PHASE

0-PHASE

SGND

MODE_PLLIN

VOUT1

PHASMD

CLKOUT

VOUT2

240-PHASE

60-PHASE

SGND

MODE_PLLIN

VOUT1

PHASMD

CLKOUT

VOUT2

300-PHASE

120-PHASE

FLOAT

MODE_PLLIN

VOUT1

PHASMD

CLKOUT

PHASMD SGND

CONTROLLER1

CONTROLLER2

CLKOUT

FLOAT

INTVCC

180

240

120

Forced Continuous Operation

In applications where fixed frequency operation is more

critical than low current efficiency, and where the low-

est output ripple is desired, forced continuous operation

should be used. Forced continuous operation can be

enabled by tying the MODE_PLLIN pin to GND. In this

mode, the inductor current is allowed to reverse during

low output loads, the COMP voltage is in control of the

current comparator threshold throughout, and the top

MOSFET always turns on with each oscillator pulse.

During start-up, the forced continuous mode is disabled,

and the inductor current is prevented from reversing until

the LTM4650-2’s output voltage is in regulation. Either

regulator can be configured for forced continuous mode.

Multiphase Operation

For output loads that demand more than 25A of current,

two outputs in LTM4650-2 or even multiple LTM4650-2s

can be paralleled to run out of phase to provide more

output current without increasing input and out-

put voltage ripples. The MODE_PLLIN pin allows the

LTM4650-2 to synchronize to an external clock (between

400kHz and 750kHz), and the internal phase-locked-

loop allows the LTM4650-2 to lock onto the incoming

clock phase as well. The CLKOUT signal can be con-

nected to the MODE_PLLIN pin of the following stage

to line up both the frequency and the phase of the entire

system. Tying the PHASMD pin to INTVCC, SGND, or

floating generates a phase difference (between

MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,

or 90 degrees respectively. A total of 12 phases can be

cascaded to run simultaneously with respect to each other

by programming the PHASMD pin of each LTM4650-2

channel to different levels. Figure 5 shows a 2-phase

design, a 4-phase design and a 6-phase design example

for clock phasing with the PHASMD table.

APPLICATIONS INFORMATION

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