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ST10F276 数据表(PDF) 40 Page - STMicroelectronics |
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ST10F276 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 229 page  Internal Flash memory ST10F276 40/229 4.5.8 Flash non volatile access protection register 1 high 4.5.9 Access protection The Flash modules have one level of access protection (access to data both in Reading and Writing): if bit ACCP of FNVAPR0 is programmed at 0, the IFlash module become access protected: data in the IFlash module can be read/written only if the current execution is from the IFlash module itself. Protection can be permanently disabled by programming bit PDS0 of FNVAPR1H, in order to analyze rejects. Allowing PDS0 bit programming only when ACCP bit is programmed, guarantees that only an execution from the Flash itself can disable the protections. Protection can be permanently enabled again by programming bit PEN0 of FNVAPR1L. The action to disable and enable again Access Protections in a permanent way can be executed a maximum of 16 times. Trying to write into the access protected Flash from internal RAM will be unsuccessful. Trying to read into the access protected Flash from internal RAM will output a dummy data. When the Flash module is protected in access, also the data access through PEC of a peripheral is forbidden. To read/write data in PEC mode from/to a protected Bank, first it is necessary to temporary unprotect the Flash module. Due to ST10 architecture, the XFLASH is seen as external memory: this makes impossible to access protect it from real external memory or internal RAM. In the following table a summary of all levels of possible Access protection is reported: in particular, supposing to enable all possible access protections, when fetching from a memory as listed in the first column, what is possible and what is not possible to do (see column headers) is shown in the table. FNVAPR1H (0x0E DFBE) NVR Delivery value: FFFFh 15 14 13 12 11 10 987 65432 10 PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 25. Flash non volatile access protection register 1 high Bit Function PEN15-0 Protections Enable 15-0 If bit PENx is programmed at 0 and bit PDSx+1 is erased at 1, the action of bit ACCP is enabled again. Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0. Table 26. Summary of access protection level Read IFLASH / Jump to IFLASH Read XFLASH /Jump to XFLASH Read FLASH Registers Write FLASH Registers Fetching from IFLASH Yes / Yes Yes / Yes Yes Yes Fetching from XFLASH No / Yes Yes / Yes Yes No Fetching from IRAM No / Yes Yes / Yes Yes No |
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