数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADS6445 数据表(PDF) 57 Page - STMicroelectronics

部件名 ADS6445
功能描述  QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
PDF  75 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADS6445 数据表(HTML) 57 Page - STMicroelectronics

Back Button ADS6445 Datasheet HTML 53Page - STMicroelectronics ADS6445 Datasheet HTML 54Page - STMicroelectronics ADS6445 Datasheet HTML 55Page - STMicroelectronics ADS6445 Datasheet HTML 56Page - STMicroelectronics ADS6445 Datasheet HTML 57Page - STMicroelectronics ADS6445 Datasheet HTML 58Page - STMicroelectronics ADS6445 Datasheet HTML 59Page - STMicroelectronics ADS6445 Datasheet HTML 60Page - STMicroelectronics ADS6445 Datasheet HTML 61Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 57 / 75 page
background image
www.ti.com
D13
(D0)
0
(D0)
D1
(0)
0
(D0)
0
(D1)
D0
(0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D7
(D8)
D8
(D7)
D6
(D9)
D5
(D10)
D4
(D11)
D3
(D12)
D2
(D13)
D13
(D2)
D6
(D7)
D10
(D3)
D3
(D10)
D7
(D6)
D0
(D13)
D12
(D1)
D12
(D1)
D5
(D8)
D9
(D4)
D2
(D11)
D11
(D2)
D4
(D9)
D8
(D5)
D1
(D12)
D13
(D0)
DataBitinLSBFirstMode
DataBitinMSBFirstMode
(1)
In16-Bitserialization,twozerobitsarepaddedtothe14-bit ADCdataontheMSBside.
OutputData
DA,DB,DC,DD
DataRate=16
Fs
´
InputClock,
CLKP/M
Freq=Fs
FrameClock,
FCLKP
Freq=1
Fs
´
BitClock – DDR,
DCLKP/M
Freq=8
Fs
´
T0225-02
OutputData
DA,DB,DC,DD
DataRate=14
Fs
´
BitClock – DDR,
DCLKP/M
Freq=7
Fs
´
SampleN
SampleN+1
2-WIRE INTERFACE - 16
× SERIALIZATION WITH DDR/SDR BIT CLOCK
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
Figure 93. 1-Wire Interface
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16
× serialization, two zero
bits are padded to the 14-bit ADC data on the MSB side and the combined 16-bit data is serialized and output
over two LVDS pairs. The data rate is 8
× Sample frequency since 8 bits are sent on each wire every clock
cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent
over the 2 wires as byte-wise or bit-wise or word-wise.
Using the 16
× serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without
requiring any modification to the receiver capture logic design.
57
Submit Documentation Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com