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ADS6445 数据表(PDF) 16 Page - STMicroelectronics

部件名 ADS6445
功能描述  QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
PDF  75 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADS6445 数据表(HTML) 16 Page - STMicroelectronics

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(3/8) AVDD
(3/8) AVDD
ToParallelPin
3R
AVDD
AVDD
GND
GND
3R
2R
(5/8) AVDD
(5/8) AVDD
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
Since some functions are controlled using both the parallel pins and serial registers, the priority between the two
is determined by a priority table (refer to Table 4).
Table 4. Priority Between Parallel Pins and Serial Registers
PIN
FUNCTIONS SUPPORTED
PRIORITY
As described in Table 8 to
Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> bit
CFG1 to CFG4
Table 11
is low, then the control voltage on these parallel pins determines the function.
Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is
PDN
Global Power Down
high, device is in global power down.
Coarse gain is controlled by register bit <COARSE GAIN>only if the <OVRD> bit is high.
Else, device has 0 dB coarse gain.
SEN
Serial Interface Enable
Internal/External Reference setting is determined by register bit <REF>.
Register bits <PATTERNS> control the sync and deskew output patterns.
Serial Interface Clock and
SCLK, SDATA
Serial Interface Data pins
Power down is determined by bit <PDN GLOBAL>
Figure 3. Simple Scheme to Configure Parallel Pins
16
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