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ADS6445 数据表(PDF) 19 Page - STMicroelectronics |
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ADS6445 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 75 page ![]() www.ti.com SERIAL INTERFACE TIMING CHARACTERISTICS RESET TIMING T0108-03 t 1 t 3 t 2 PowerSupply AVDD,LVDD RESET SEN ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Typical values at 25 °C, min and max values across the full temperature range T MIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted. PARAMETER MIN TYP MAX UNIT fSCLK SCLK Frequency, fSCLK = 1/tSCLK > DC 20 MHz tSLOADS SEN to SCLK Setup time 25 ns tSLOADH SCLK to SEN Hold time 25 ns tDSU SDATA Setup time 25 ns tDH SDATA Hold time 25 ns Time taken for register write to take effect after 16th SCLK falling edge 100 ns Typical values at 25 °C, min and max values across the full temperature range T MIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted. PARMATER CONDITIONS MIN TYP MAX UNIT Delay from power-up of AVDD and LVDD to RESET pulse t1 Power-on delay time 5 ms active t2 Reset pulse width Pulse width of active RESET signal 10 ns t3 Register write delay time Delay from RESET disable to SEN active 25 ns tPO Power-up delay time Delay from power-up of AVDD and LVDD to output stable 6.5 ms Figure 5. Reset Timing 19 Submit Documentation Feedback |
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