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TSC2007

SBAS405 – MARCH 2007

OVERVIEW (continued)

fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving

data as a receiver. The device that controls the message is called a master. The devices that are controlled by

the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL),

controls the bus access, and generates the START and STOP conditions. The TSC2007 operates as a slave on

The following bus protocol has been defined (see Figure 29):

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy

Both data and clock lines remain HIGH.

Start Data Transfer

A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a

START condition.

Stop Data Transfer

A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the

STOP condition.

Data Valid

The state of the data line represents valid data, when, after a START condition, the data line is

stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of

data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited and is

determined by the master device. The information is transferred byte-wise and each receiver

acknowledges with a ninth-bit.

rate), and a high-speed mode (1.7MHz or 3.4MHz clock rate) are each defined. The TSC2007

works in all three modes.

Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception

of each byte. The master device must generate an extra clock pulse that is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in

such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock

pulse. Of course, setup and hold times must be taken into account. A master must signal an end of

data to the slave by not generating an acknowledge bit on the last byte that has been clocked out

of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate

the STOP condition.

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