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AS7221

UART Command Interface

Datasheet

• PUBLIC

DS000479

• v4-00 • 2019-Jun-28

│ 29

9.2

UART Protocol

Figure 26:

UART Protocol

9.3

SPI Timing Characteristics

The AS7221 contains a serial UART interface to connect to a Flash memory. An Overview can be

found in Figure 30. The required timing characteristics for a serial interface is shown in Figure 28 and

in Figure 29 accordingly. If a Flash memory is used for debug purposes which is not listed in Figure 30

it should be ensured that the SPI timing is achieved. Contact ams for requests to support/verify

additional Flash devices beyond those listed in the most current device verification listing.

Figure 27:

AS7221 SPI Timing Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

Clock Frequency

MHz

tSCK_H

Clock High Time

tSCK_L

Clock Low Time

tSCK_RISE

SCK Rise Time

tSCK_FALL

SCK Fall Time

TCSN_S

CSN Setup Time

Time between CSN high-low transition

to first SCK high transition

tCSN_H

CSN Hold Time

Time between last SCK falling edge

and CSN low-high transition

tCSN_DIS

CSN Disable Time

tDO_S

Data-Out Setup Time

After Tbit/2: Sampling of Start Bit

Start Bit

Stop Bit

Data Bits

Start

Next Start

Start Bit detected

Tbit=1/Baud Rate

Always Low

Always High

After Tbit: Sampling of Data

Sample Points

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