TMD2621 datasheet(20/59 Pages) OSRAM

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Datasheet, Public

Page 19

[v4-00] 2023-Apr-12

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TMD2621 − Register Overview

PERS Register (Address 0x8C)

Figure 26:

PERS Register

The frequency of consecutive proximity channel results outside

of threshold limits are counted; this count value is compared

against the PPERS value. If the counter is equal to the PPERS

value an interrupt is asserted. Any time a proximity channel

result is inside the threshold values the counter is cleared.

CFG0 Register (Address 0x8D)

Figure 27:

CFG0 Register

Addr: 0x8C

PERS

Bit

Bit Name

Default

Access

Bit Description

7:4

PPERS

0000

This register sets the proximity persistence filter.

Value

Interrupt

Every proximity cycle

Any value outside proximity thresholds

2 consecutive proximity values out of range

3 consecutive proximity values out of range

…….

15 consecutive proximity values out of range

3:0

Reserved

0000

Reserved. Must be set to default value.

Addr: 0x8D

CFG0

Bit

Bit Name

Default

Access

Bit Description

ENAB_16_

BIT_OP

0RW

Enables output of PDATA to be a 16-bit value when

APC is ON. See PDATA (0xF4 and 0xF5) for details.

6:4

Reserved

001

Reserved. Must be set to default value.

3PWLONG

When PWLONG (PROX Wait Long) is asserted the wait

period as set by PWTIME is increased by a factor of 12.

2:0

Reserved

000

Reserved. Must be set to default value.

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