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TMD3721 数据表(PDF) 41 Page - OSRAM GmbH |
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TMD3721 数据表(HTML) 41 Page - OSRAM GmbH |
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41 / 89 page  Page 40 Datasheet, Public Document Feedback [v3-00] 2023-May-26 TMD3721 − Register O ver view 0 PLDRIVER0_PAD_ SHORT_VDD_FAIL 0R When the flag is set, it indicates that the VDD check during eye safety check failed for PLDRIVER0. The PLDRIVER0 is disabled (no pulses are sent) in case of failure but the proximity timing is maintained. When ESIEN is 1, an interrupt is generated in the final state after PROX_DATA_AVG is complete. The flag is cleared when PON is made 0. Writing a 1 to this field will clear the flag. To enable clear-by-read function, INT_READ_CLEAR in the register CFG3 must be set to 1. Addr: 0x9F EYE_SAFETY_STATUS Bit Bit Name Default Access Bit Description |
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