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AD9516-2/PCBZ 数据表(PDF) 55 Page - Analog Devices

部件名 AD9516-2/PCBZ
功能描述  14-Output Clock Generator with Integrated 2.2 GHz VCO
PDF  84 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9516-2/PCBZ 数据表(HTML) 55 Page - Analog Devices

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AD9516-2
Rev. 0 | Page 55 of 84
CS
SCLK
SDIO
tHI
tLO
tCLK
tS
tDS
tDH
tC
BIT N
BIT N + 1
Figure 67. Serial Control Port Timing—Write
Table 50. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
tS
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
tC
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
tHI
Minimum period that SCLK should be in a Logic High state
tLO
Minimum period that SCLK should be in a Logic Low state
tDV
SCLK to valid SDIO and SDO (see Figure 65)



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