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AD9516-2/PCBZ 数据表(PDF) 8 Page - Analog Devices |
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AD9516-2/PCBZ 数据表(HTML) 8 Page - Analog Devices |
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8 / 84 page  AD9516-2 Rev. 0 | Page 8 of 84 Parameter Min Typ Max Unit Test Conditions/Comments Delay Variation with Temperature Short Delay Range5 Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C Long Delay Range5 Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to A for noninverting, and B for inverting. 3 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation. CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, OUTPUT = 1 GHz Input slew rate > 1 V/ns Divider = 1 @ 10 Hz Offset −109 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −139 dBc/Hz @ 100 kHz Offset −144 dBc/Hz @ 1 MHz Offset −146 dBc/Hz @ 10 MHz Offset −147 dBc/Hz @ 100 MHz Offset −149 dBc/Hz CLK = 1 GHz, OUTPUT = 200 MHz Input slew rate > 1 V/ns Divider = 5 @ 10 Hz Offset −120 dBc/Hz @ 100 Hz Offset −126 dBc/Hz @ 1 kHz Offset −139 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1.6 GHz, OUTPUT = 800 MHz Input slew rate > 1 V/ns Divider = 2 @ 10 Hz Offset −103 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −120 dBc/Hz @ 10 kHz Offset −127 dBc/Hz @ 100 kHz Offset −133 dBc/Hz @ 1 MHz Offset −138 dBc/Hz @ 10 MHz Offset −147 dBc/Hz @ 100 MHz Offset −149 dBc/Hz |
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