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MFS5600AMBAFES 数据表(PDF) 39 Page - NXP Semiconductors

部件名 MFS5600AMBAFES
功能描述  Automotive buck regulator and controller with voltage monitors and watchdog timer
PDF  118 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MFS5600AMBAFES 数据表(HTML) 39 Page - NXP Semiconductors

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NXP Semiconductors
FS5600
Automotive buck regulator and controller with voltage monitors and watchdog timer
OTP_PGOOD1_DELAY[2:0]
OTP_PGOOD2_DELAY[2:0]
OTP_GPO1_DELAY[2:0]
OTP_GPO2_DELAY[2:0]
OTP_GPO3_DELAY[2:0]
Delay duration (µs)
000
GPO1/2/3 held low through power-up.
No additional delay for PGOOD1/2 release.
001
250
010
500
011
1000
100
2000
101
4000
110
8000
111
16000
Table 31. PGOOD1/2, GPIO1/2/3 delay selection
15.5 MODE pin
The MODE/SYNCIN pin can be configured as a MODE input via OTP by setting OTP_MODE_SYNCINB = 1.
The switching mode of SW1 and SW2 regulators can be changed by toggling with MODE pin.
When MODE = 0, SW1 and SW2 operate in continuous PWM mode.
When MODE = 1, SW1 and SW2 operate in PFM mode. In this condition, several internal circuits are turned off
to achieve low quiescent current operation. PGOOD1 and PGOOD2 outputs indicate regulation status of SW1
and SW2 respectively in this condition.
Note: OTP_ULPM_EN = 1 for all QM devices to achieve the low quiescent current. OTP_ULPM_EN may be
set to 0 or 1 for ASIL B and Enhanced ASIL B variations to achieve different behavior. See Section 17.13.9 for
details.
15.6 I2C communication
Communication with the FS5600 is done through I2C, and it supports high-speed operation mode with up to 3.4
MHz operation. SDA and SCL are pulled up to VDDIO typically with 2.2 kΩ resistors for 400 kHz operation, and
500 Ω for 3.4 MHz operation.
Refer to UM10204, I 2C-bus specification and user manual for detailed information on the digital I2C
communication protocol implementation. The FS5600 is designed to operate as a slave device during I2C
communication. The default I2C device address is set by the OTP_I2C_ADD[2:0].
OTP_I2C_ADD[2:0]
Device address
000
0x18 (Default)
001
0x19
010
0x1A
011
0x1B
100
0x1C
101
0x1D
Table 32. I2C address selection
FS5600
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 4 — 29 April 2024
39 / 118



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