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MFS5600AMBAFES 数据表(PDF) 46 Page - NXP Semiconductors |
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MFS5600AMBAFES 数据表(HTML) 46 Page - NXP Semiconductors |
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46 / 118 page ![]() NXP Semiconductors FS5600 Automotive buck regulator and controller with voltage monitors and watchdog timer When an error occurs on the Watchdog refresh with an error on the timing, the bit "BAD_WD_TIMING" is set for diagnostics. When an error occurs on the Watchdog refresh with an error on the data, the bit "BAD_WD_DATA" is set for diagnostics. The duration of the watchdog window is configurable from 1 ms to 1024 ms with the WD_WINDOW [3:0] bits. The new watchdog window is effective after the next watchdog refresh. The watchdog window may be set to infinite. The WD_WINDOW[3:0] has a complimentary register NOT_WD_WINDOW[3:0] which must be written with the complimentary value for the input to take effect. This is to prevent erroneous communication from causing negative system impact. The initial watchdog window is set to 1024 ms until the first refresh by default. This is to allow time for the MCU to boot up and refresh the watchdog for the first time. The 1024 ms initial window is available every time the Watchdog starts. WD_WINDOW[3:0] Watchdog window period 0000 DISABLE (during INIT_FS only) 0001 1.0 ms 0010 2.0 ms 0011 (default) 3.0 ms 0100 4.0 ms 0101 6.0 ms 0110 8.0 ms 0111 12 ms 1000 16 ms 1001 24 ms 1010 32 ms 1011 64 ms 1100 128 ms 1101 256 ms 1110 512 ms 1111 1024 ms Table 38. Watchdog window period configuration The duty cycle of the watchdog window is configurable from 31.25 % to 68.75 % with the WDW_DC [2:0] bits. The new duty cycle is effective after the next watchdog refresh. WDW_DC [2:0] CLOSED window OPEN window 000 31.25 % 68.75 % 001 37.5 % 62.5 % 010 (default) 50 % 50 % 011 62.5 % 37.5 % 100 68.75 % 31.25 % Table 39. Watchdog window duty cycle configuration FS5600 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 4 — 29 April 2024 46 / 118 |
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