MFS5600AMBAFES datasheet(53/118 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

Function

Option

When OTP_SW1_UV_PGOODx = 1

an under-voltage event on SW1 causes PGOODx to be

asserted.

When OTP_SW2_OV_PGOODx = 1

an over-voltage event on SW2 causes PGOODx to be

asserted.

When OTP_SW2_UV_PGOODx = 1

an under-voltage event on SW2 causes PGOODx to be

asserted.

When OTP_VMON1_OV_PGOODx = 1

an over-voltage event on VMON1 causes PGOODx to be

asserted.

When OTP_VMON1_UV_PGOODx = 1

an under-voltage event on VMON1 causes PGOODx to be

asserted.

When OTP_VMON2_OV_PGOODx = 1

an over-voltage event on VMON2 causes PGOODx to be

asserted.

When OTP_VMON2_UV_PGOODx = 1

an under-voltage event on VMON2 causes PGOODx to be

asserted.

When OTP_VMON3_OV_PGOODx = 1

an over-voltage event on VMON3 causes PGOODx to be

asserted.

When OTP_VMON3_UV_PGOODx = 1

an under-voltage event on VMON3 causes PGOODx to be

asserted.

When OTP_VMON4_OV_PGOODx = 1

an over-voltage event on VMON4 causes PGOODx to be

asserted.

When OTP_VMON4_UV_PGOODx = 1

an under-voltage event on VMON4 causes PGOODx to be

asserted

When OTP_FCCU_ERR_PGOODx = 1

an FCCU error (FCCU1, FCCU2, or FCCU12) causes

PGOODx to be pulsed low for 8 ms.

Table 45. PGOOD1/2 programmable reactions...continued

When any of the OTP bits listed above is set to 0, a corresponding fault on the regulator/monitor has no impact

on the PGOODx pin.

The delay for conditions to be satisfied and PGOODx being released is programmable using the

OTP_PGOODx_DELAY[2:0] bits. See Table 31 for details.

After PGOODx is de-asserted and there is an OV or UV fault, the fault is de-bounced and PGOODx is asserted.

17.6.1 Watchdog impact on PGOOD1/2

When OTP_WD_PGOODx = 1, a watchdog failure causes the PGOODx pin to toggle low for 10 ms. The

watchdog is stopped when PGOODx is low and is reset at the end of the 10 ms.

The FLT_ERR_CNT is incremented by 1 for every PGOODx toggle due to a watchdog failure.

During the initial 1024 ms window, a single watchdog error (bad refresh or no refresh for 1024ms) is considered

a Watchdog failure and the assigned PGOODx pin is toggled.

After the initial 1024 ms window, a 'watchdog failure' when WD_ERR_CNT >= WD_ERR_LIMIT.

Example behavior: Suppose OTP_WD_PGOODx = 1; if a watchdog error occurs during the 1024 ms initial

period, PGOODx pin is toggled, the FLT_ERR_CNT incremented, and the watchdog restarted. This allows the

system MCU to reset and try refreshing the watchdog again. If the MCU fails continuously, the FLT_ERR_CNT

reaches its limit and the FS5600 may transition to the deep fail-safe state (if enabled) to prevent a continuous

fault loop. While in the NORMAL STATE, if a watchdog failure occurs (watchdog error count reaches limit),

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

53 / 118

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