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MPC855T 数据表(PDF) 69 Page - Freescale Semiconductor, Inc |
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MPC855T 数据表(HTML) 69 Page - Freescale Semiconductor, Inc |
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69 / 80 page ![]() MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 69 FEC Electrical Characteristics Figure 71. MII Receive Signal Timing Diagram 13.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN, MII_TX_ER, MII_TX_CLK) The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%. Table 30 provides information on the MII transmit signal timing. Figure 72 shows the MII transmit signal timing diagram. Table 30. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25 M7 MII_TX_CLK pulse width high 35 65% MII_TX_CLK period M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period M1 M2 MII_RX_CLK (Input) MII_RXD[3:0] (Inputs) MII_RX_DV MII_RX_ER M3 M4 |
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