MPC855T datasheet(20/80 Pages) FREESCALE

20 / 80 page

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconductor

Bus Signal Timing

Figure 2 is the control timing diagram.

Figure 2. Control Timing

Figure 3 provides the timing for the external clock.

The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.

The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified

in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17.

10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior

specified in Figure 20.

CLKOUT

Outputs

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

Outputs

2.0 V

0.8 V

2.0 V

0.8 V

Inputs

2.0 V

0.8 V

2.0 V

0.8 V

Inputs

2.0 V

0.8 V

2.0 V

0.8 V

Maximum output delay specification

Minimum output hold time

Minimum input setup time specification

Minimum input hold time specification

MPC855T 数据表(PDF) 20 Page - Freescale Semiconductor, Inc

MPC855T 数据表(HTML) 20 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载

链接网址

MPC855T 数据表(PDF) 20 Page - Freescale Semiconductor, Inc

MPC855T 数据表(HTML) 20 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表 下载

链接网址

数据表下载