MPC8271VRM datasheet(57/60 Pages) FREESCALE

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MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5

Freescale Semiconductor

Document Revision History

11 Document Revision History

Table 22 lists significant changes between revisions of this hardware specification.

Table 22. Document Revision History

Revision

Date

Substantive Changes

1.5

12/2006

• Section 6, “AC Electrical Characteristics,” removed deratings statement and clarified AC

timing descriptions.

1.4

05/2006

• Added row for 133 MHz configurations to Table 7.

1.3

02/2006

• Inserted Section 6.3, “JTAG Timings.”

1.2

09/2005

• Added 133-MHz to the list of frequencies in the opening sentence of Section 6, “AC Electrical

Characteristics”.

• Added 133 MHz columns to Table 9, Table 10, Table 11, and Table 12.

• Added footnote 2 to Table 12.

• Added the conditions note directly above Table 11.

1.1

01/2005

• Modification for correct display of assertion level (“overbar”) for some signals

1.0

12/2004

• Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier values

• Section 2: removed voltage tracking note

• Table 3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset

• Table 4: Updated VDD and VCCSYN to 1.425 V - 1.575 V

• Table 5: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external

pullup removed.

• Section 4.6: Updated description of layout practices

• Table 5: Note 3 added regarding IIC compatibility

• Table 7: Updated nominal and maximum power dissipation values

• Table 8: updated PCI impedance to 27

Ω, updated 60x and MEMC values and added note to

reflect configurable impedance

• Section 6: Added sentence providing derating factor

• Section 6.1: added Note: Rise/Fall Time on CPM Input Pins

• Table 9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41,

sp42, sp43, sp42a

• Table 10: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22

• Section 6.2: added spread sprectrum clocking note

• Section 6.2: added CLKIN jitter note

• Table 11: combined specs sp11 and sp11a

• Table 12: sp30 Data Bus minimum delay values changed to 0.8

• Section 7: unit of ns added to Tval notes

• Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp

devices, 175 MHz extended temp; CPM Fmin of 120 MHz.

• Section 7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin

of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.

• Table 20: correct superscript of footnote number after pin AD22

• Table 20: remove DONE3 from PC12

• Table 20: signals referring to TDMs C2 and D2 removed

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