MPC8271VRM datasheet(19/60 Pages) FREESCALE

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MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5

Freescale Semiconductor

AC Electrical Characteristics

Figure 8 shows PIO and timer signals.

Figure 8. PIO and Timer Signal Diagram

6.2

SIU AC Characteristics

Table 11 lists SIU input characteristics.

NOTE: CLKIN Jitter and Duty Cycle

The CLKIN input to the MPC8272 should not exceed +/– 150 psec. This

represents total input jitter—the combination of short term (peak-to-peak)

and long term (cumulative). The duty cycle of CLKIN should not exceed the

ratio of 40:60.

NOTE: Spread Spectrum Clocking

Spread spectrum clocking is allowed with 1% input frequency down-spread

at maximum 60 KHz modulation rate regardless of input frequency.

NOTE: PCI AC Timing

The MPC8272 meets the timing requirements of PCI Specification Revision

2.2. Refer to Section 7, “Clock Configuration Modes” and “Note: Tval

(Output Hold)” to determine if a specific clock configuration is compliant.

Sys clk

PIO/IDMA/TIMER[TGATE assertion] input signals

IDMA output signals

sp22

sp23

sp42/sp43

TIMER(sp42/43)/ PIO(sp42a/sp43a)

sp42a/sp43a

output signals

sp42/sp43

TIMER input signal [TGATE deassertion]

sp22

sp23

Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

(See note)

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