Figure 38. Startup time schematic

+

-

OUT

VIN+

Vcc

12 V

VIN-

Reference

voltage 0.6V

CMPOUT

RESET

-

+

CMPIN

GND

Vcc

5 V

Rp = 5.1 k Ω

Rs = 10 m Ω

Cd = 100 nF

Figure 39. Startup time with a decoupling capacitance of

100 nF

0

100µ

200µ

300µ

400µ

500µ

600µ

0

100µ

200µ

300µ

400µ

500µ

600µ

-3

-2

-1

0

1

2

3

4

5

6

-2

0

2

4

6

Vcc

Vsense=70mV,

Vcc=5V, Vicm=12V,

T=25°C

Comparator Output

Time (s)

Current sensing Output

5.9

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the current sensing, load, and

power supply. It is good practice to use short and wide PCB traces to minimize voltage drops and parasitic

inductance.

When using a shunt resistance lower than 1 Ω, it is important to use a 4-wire connection technique to sense the

current as described in the schematic below. Effectively, this technique allows pairs of current-carrying and

voltage-sensing electrodes to separate, and to take more accurate measurements by eliminating the lead and

contact resistance from the measurements.

It is also important to treat the track connected to the input pin of the TSC20x as a differential pair. Thus, it must

have the same length and width, and ideally be placed on the same PCB plane, and above all, it must be routed

as far as possible from noisy sources. As this track carries the input bias current in a range of tens of µA, it can be

designed small, but always taking into account resistivity. Any via in these input tracks are non-recommended to

avoid any parasitic resistance in this path.

To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top

layer ground planes together in many locations is often used.

A ground plane generally helps to reduce EMI, which is why it is generally recommended to use a multilayer PCB,

and use the ground planes as a shield to protect the internal track. In this case, pay attention to separate the

digital from the analog ground and avoid any ground loop. To minimize EMI impact, it is important to reduce loop

areas, which act as antennas.

Figure 40 suggests a possible routing for the TSC200, to minimize as much as possible a parasitic effect.

TSC200, TSC201, TSC202

PCB layout recommendations

DS13882 - Rev 2

page 20/34