List of figures

Figure 1.

Block diagram .................................................................... 2

Figure 2.

Pin connections (top view) ............................................................ 2

Figure 3.

Typical comparator hysteresis.......................................................... 6

Figure 4.

Gain vs. frequency (CL = 1000 pF) ...................................................... 7

Figure 5.

Gain vs. frequency (CL = 100 pF) ....................................................... 7

Figure 6.

Gain plot ........................................................................ 7

Figure 7.

CMRR and PSRR vs. frequency ........................................................ 7

Figure 8.

Output error vs. Vsense............................................................... 8

Figure 9.

Output error vs. common-mode voltage ................................................... 8

Figure 10.

Output current vs. output voltage at VCC = 2.7 V ............................................. 8

Figure 11.

Output current vs. output voltage at VCC = 12 V ............................................. 8

Figure 12.

Quiescent current vs. output voltage ..................................................... 8

Figure 13.

Quiescent current vs. common-mode voltage ............................................... 8

Figure 14.

Output short-circuit current vs. supply voltage............................................... 9

Figure 15.

Step response for 20 to 30 mV Vsense G = 20 ............................................... 9

Figure 16.

Step response for 20 to 110 mV Vsense G = 20 .............................................. 9

Figure 17.

Step response for 90 to 100 mV Vsense G = 20 .............................................. 9

Figure 18.

Step response for 20 to 30 mV Vsense G = 50 ............................................... 9

Figure 19.

Step response for 20 to 110 mV Vsense G = 50 .............................................. 9

Figure 20.

Step response for 90 to 100 mV Vsense G = 50 ............................................. 10

Figure 21.

Step response for 20 to 110 mV Vsense G = 100 ............................................ 10

Figure 22.

Comparator VOL vs. ISINK............................................................ 10

Figure 23.

Comparator trip points vs. VCC ........................................................ 10

Figure 24.

Comparator trip points vs. temperature .................................................. 11

Figure 25.

Comparator reset voltage vs. VCC ...................................................... 11

Figure 26.

Comparator propagation delay vs. overdrive voltage ......................................... 11

Figure 27.

Comparator propagation delay vs. temperature............................................. 11

Figure 28.

Comparator propagation delay ........................................................ 11

Figure 29.

Simplified diagram when Vicm > 40% VCC ................................................ 12

Figure 30.

Input bias current vs. Vsense for a Vicm = 80 V .............................................. 13

Figure 31.

Simplified diagram when Vicm < 40% VCC ................................................ 14

Figure 32.

Input bias current vs. Vsense for a Vicm = -16 V ............................................. 14

Figure 33.

VOUT when Vsense = 0 V, VCC = 5 V, Vicm = 0 V............................................. 15

Figure 34.

VOUT when Vsense = 0 V, VCC = 5 V, Vicm = 12 V ............................................ 15

Figure 35.

Input voltage offset over Vicm and temperature ............................................. 15

Figure 36.

Input referred noise vs. frequency ...................................................... 17

Figure 37.

Stability criteria with a serial resistor at VCC = 5 V ........................................... 19

Figure 38.

Startup time schematic ............................................................. 20

Figure 39.

Startup time with a decoupling capacitance of 100 nF ........................................ 20

Figure 40.

Recommended layout .............................................................. 21

Figure 41.

EMIRR on pin+ ................................................................... 21

Figure 42.

EMIRR on pin- ................................................................... 21

Figure 43.

Negative overvoltage recovery VCC = 5 V................................................. 22

Figure 44.

Positive overvoltage recovery VCC = 5 V ................................................. 22

Figure 45.

Comparator latching capability ........................................................ 22

Figure 46.

Typical OCP application............................................................. 23

Figure 47.

TSC200 response time to an overcurrent event ............................................ 24

Figure 48.

CMPOUT at startup when CMPIN < 0.6 V ................................................. 24

Figure 49.

CMPOUT at startup when CMPIN > 0.6 V ................................................. 24

Figure 50.

TSC200 used to drive and protect a power amplifier ......................................... 25

TSC200, TSC201, TSC202

List of figures

DS13882 - Rev 2

page 32/34