M28W320FCT datasheet(12/69 Pages) STMICROELECTRONICS

12 / 69 page

Signal descriptions

M28W320FCT, M28W320FCB

12/69

Signal descriptions

See Figure 1: Logic Diagram and Figure 1: Signal Names, for a brief overview of the signals

connected to this device.

2.1

Address inputs (A0-A20)

The Address Inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the internal state machine.

2.2

Data input/output (DQ0-DQ15)

The Data I/O outputs the data stored at the selected address during a Bus Read operation

or inputs a command or the data to be programmed during a Write Bus operation.

2.3

Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active

mode. When Chip Enable is at VIH the memory is deselected, the outputs are high

impedance and the power consumption is reduced to the stand-by level.

2.4

Output Enable (G)

The Output Enable controls data outputs during the Bus Read operation of the memory.

2.5

Write Enable (W)

The Write Enable controls the Bus Write operation of the memory’s Command Interface.

The data and address inputs are latched on the rising edge of Chip Enable, E, or Write

Enable, W, whichever occurs first.

2.6

Write Protect (WP)

Write Protect is an input that gives an additional hardware protection for each block. When

Write Protect is at VIL, the Lock-Down is enabled and the protection status of the block

cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the block

can be locked or unlocked. (refer to Table 7: Read Protection Register and Lock Register).

2.7

Reset (RP)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the

memory is in reset mode: the outputs are high impedance and the current consumption is

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