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SCA61T 数据表(PDF) 5 Page - VTI technologies |
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SCA61T 数据表(HTML) 5 Page - VTI technologies |
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5 / 18 page ![]() SCA61T Series VTI Technologies Oy Subject to changes 5/18 www.vti.fi Doc. nr. 8261900 Rev.A CSB SCK MOSI MISO TLS1 TCH THOL TSET TVAL1 TVAL2 TLZ TLS2 TLH MSB in MSB out LSB in LSB out DATA out DATA in TCL 1.6 SPI Interface Timing Specifications Parameter Conditions Symbol Min. Typ. Max. Unit Terminal CSB, SCK Time from CSB (10%) to SCK (90%) TLS1 120 ns Time from SCK (10%) to CSB (90%) TLS2 120 ns Terminal SCK SCK low time Load capacitance at MISO < 2 nF TCL 1 µs SCK high time Load capacitance at MISO < 2 nF TCH 1 µs Terminal MOSI, SCK Time from changing MOSI (10%, 90%) to SCK (90%). Data setup time TSET 30 ns Time from SCK (90%) to changing MOSI (10%,90%). Data hold time THOL 30 ns Terminal MISO, CSB Time from CSB (10%) to stable MISO (10%, 90%). Load capacitance at MISO < 15 pF TVAL1 10 100 ns Time from CSB (90%) to high impedance state of MISO. Load capacitance at MISO < 15 pF TLZ 10 100 ns Terminal MISO, SCK Time from SCK (10%) to stable MISO (10%, 90%). Load capacitance at MISO < 15 pF TVAL2 100 ns Terminal CSB Time between SPI cycles, CSB at high level (90%) TLH 15 µs When using SPI commands RDAX, RDAY, RWTR: Time between SPI cycles, CSB at high level (90%) TLH 150 µs Figure 2. Timing diagram for SPI communication |
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