SCF5249 datasheet(41/56 Pages) FREESCALE

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Electrical Characteristics

SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Freescale Semiconductor

Figure 13. I2C Timing Definition

Stop Condition Setup Time

tbd

—

bus clocks

Table 27. I2C-Bus Output Timing Specifications Between SCL and SDA

Num

Characteristic

Units

Min

Max

M11

Start Condition Hold Time

tbd

—

bus clocks

M21

Clock Low Period

tbd

—

bus clocks

M32

SCL/SDA Rise Time

(VIL= 0.5 V to VIH = 2.4 V)

—

tbd

mSec

M41

Data Hold Time

tbd

—

bus clocks

M53

SCL/SDA Fall Time

(VIH= 2.4 V to VIL = 0.5 V)

—

tbd

nSec

M61

Clock High time

tbd

—

bus clocks

M71

Data Setup Time

tbd

—

bus clocks

M81

Start Condition Setup Time

(for repeated start condition only)

tbd

—

bus clocks

M91

Stop Condition Setup Time

tbd

—

bus clocks

Note: Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed

with the maximum frequency (MFDR = 0x20) will result in minimum output timings as shown in the above

table. The MBUS interface is designed to scale the actual data transition time to move it to the middle of

the SCL low period. The actual position is affected by the prescale and division values programmed into

the MFDR; however, numbers given in the above table are the minimum values.

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the

time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up

resistor values.

Specified at a nominal 20 pF load.

Table 26. I2C-Bus Input Timing Specifications Between SCL and SDA

Num

Characteristic

Units

Min

Max

SCL

SDA

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