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SCF5249VM140 数据表(PDF) 25 Page - Freescale Semiconductor, Inc

部件名 SCF5249VM140
功能描述  Integrated ColdFire Microprocessor
PDF  56 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

SCF5249VM140 数据表(HTML) 25 Page - Freescale Semiconductor, Inc

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Signal Descriptions
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
25
NOTE
JTAG operation will override the HI_Z pin.
8.19.3 Processor Clock Output
The internal PLL generates this PSTCLK/GPO63 and output signal, and is the processor clock output that
is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The
PSTCLK/GPO63 is at the same frequency as the core processor and cache memory. The frequency will be
twice the bus clock (SCLK) frequency.
8.19.4 Debug Data
The debug data pins, DDATA0_GPIO0, DDATA1_GPIO1, DDATA2_GPIO2, and DDATA3_GPIO4, are
four bits wide. This nibble-wide bus displays captured processor data and break-point status.



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