SCF5249VM140 datasheet(42/56 Pages) FREESCALE

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SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Electrical Characteristics

Freescale Semiconductor

Figure 14. I2C and System Clock Timing Relationship

Table 28. I2C Output Bus Timings

Num

Characteristic

Units

Min

Max

M103

SCL, SDA Valid to SCLK (input setup)

tbd

—

nSec

M11

SCLK to SCL, SDA Invalid (input hold)

tbd

—

nSec

M121

SCLK to SCL, SDA Low (output valid)

—

tbd

nSec

M132

SCLK to SCL, SDA Invalid (output hold)

tbd

—

nSec

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this

specification applies only when SCL or SDA are driven low by the processor. The time required for SCL or

SDA to reach a high level depends on external signal capacitance and pull-up resistor values.

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this

specification applies only when SCL or SDA are actively being driven or held low by the processor.

SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular

clock is required.

Table 29. General-Purpose I/O Port AC Timing Specifications

Num

Characteristic

Units

Min

Max

GPIO Valid to SCLK (input setup)

tbd

—

nSec

SCLK to GPIO Invalid (input hold)

tbd

—

nSec

SCLK

SCL, SDA IN

SCL, SDA OUT

M10

M11

M12

M13

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