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MCP1702 数据表(PDF) 12 Page - Microchip Technology

部件名 MCP1702
功能描述  250 mA Low Quiescent Current LDO Regulator
PDF  26 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP1702 数据表(HTML) 12 Page - Microchip Technology

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MCP1702
DS22008B-page 12
© 2007 Microchip Technology Inc.
5.0
FUNCTIONAL DESCRIPTION
The MCP1702 CMOS LDO linear regulator is intended
for applications that need the lowest current consump-
tion while maintaining output voltage regulation. The
operating continuous load range of the MCP1702 is
from 0mA to 250mA (VR ≥ 2.5V). The input operating
voltage range is from 2.7V to 13.2V, making it capable
of operating from two or more alkaline cells or single
and multiple Li-Ion cell batteries.
5.1
Input
The input of the MCP1702 is connected to the source
of the P-Channel PMOS pass transistor. As with all
LDO circuits, a relatively low source impedance (10
Ω)
is needed to prevent the input impedance from causing
the LDO to become unstable. The size and type of the
capacitor needed depends heavily on the input source
type (battery, power supply) and the output current
range of the application. For most applications (up to
100 mA), a 1 µF ceramic capacitor will be sufficient to
ensure circuit stability. Larger values can be used to
improve circuit AC performance.
5.2
Output
The maximum rated continuous output current for the
MCP1702 is 250 mA (VR ≥ 2.5V). For applications
where VR < 2.5V, the maximum output current is
200 mA.
A minimum output capacitance of 1.0 µF is required for
small signal stability in applications that have up to
250 mA output current capability. The capacitor type
can be ceramic, tantalum or aluminum electrolytic. The
esr range on the output capacitor can range from 0
Ω to
2.0
Ω.
5.3
Output Rise time
When powering up the internal reference output, the
typical output rise time of 500 µs is controlled to
prevent overshoot of the output voltage. There is also
a startup delay time that ranges from 300 µs to 800 µs
based on loading. The startup time is separate from
and precedes the Output Rise Time. The total output
delay is the Startup Delay plus the Output Rise time.



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