ADAU1761BCPZ-R7 datasheet(60/92 Pages) AD

60 / 92 page

Data Sheet

ADAU1761

CONTROL REGISTERS

analog.com

Rev. F | 60 of 92

Table 61. ALC Control 2 Register (Continued)

Bits

Bit Name

Description

0010

96 ms

0011

192 ms

0100

384 ms

0101

768 ms

0110

1.54 sec

0111

3.07 sec

1000

6.14 sec

1001

12.29 sec

1010

24.58 sec

1011

49.15 sec

1100

98.30 sec

1101

196.61 sec

1110

393.22 sec

1111

786.43 sec

R14: ALC Control 3, 16,404 (0x4014)

Table 62.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

NGTYP[1:0]

NGEN

NGTHR[4:0]

Table 63. ALC Control 3 Register

Bits

Bit Name

Description

[7:6]

NGTYP[1:0]

Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant PGA gain, mute the ADC

output, fade the PGA gain to the minimum gain value, or fade then mute.

Setting

Noise Gate

Hold PGA constant (default)

Mute ADC output (digital mute)

Fade to PGA minimum value (analog fade)

Fade then mute (analog fade/digital mute)

NGEN

Noise gate enable.

0 = disabled (default).

1 = enabled.

[4:0]

NGTHR[4:0]

Noise gate threshold. When the input signal falls below the threshold for 250 ms, the noise gate is activated. A 1 LSB increase corresponds

to a −1.5 dB change. See Table 150 for a complete list of the threshold settings.

Setting

Threshold

00000

−76.5 dB (default)

00001

−75 dB

…

11110

−31.5 dB

11111

−30 dB

R15: Serial Port Control 0, 16,405 (0x4015)

Table 64.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SPSRS

LRMOD

BPOL

LRPOL

CHPF[1:0]

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