ADAU1761BCPZ-R7 datasheet(21/92 Pages) AD

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Data Sheet

ADAU1761

THEORY OF OPERATION

analog.com

Rev. F | 21 of 92

The ADAU1761 is a low power audio codec with an integrated

stream-oriented DSP core, making it an all-in-one package that

offers high quality audio, low power, small size, and many advanced

features. The stereo ADC and stereo DAC each have an SNR of at

least +98 dB and a THD + N of at least −90 dB. The serial data port

is compatible with I2S, left-justified, right-justified, and TDM modes

for interfacing to digital audio data. The operating voltage range is

1.8 V to 3.65 V, with an on-board regulator generating the internal

digital supply voltage.

The record signal path includes very flexible input configurations

that can accept differential and single-ended analog microphone

inputs as well as a digital microphone input. A microphone bias

pin provides seamless interfacing to electret microphones. Input

configurations can accept up to six single-ended analog signals or

variations of stereo differential or stereo single-ended signals with

two additional auxiliary single-ended inputs. Each input signal has

its own programmable gain amplifier (PGA) for volume adjustment

and can be routed directly to the playback path output mixers,

bypassing the ADCs. An automatic level control (ALC) can also be

implemented to keep the recording volume constant.

The ADCs and DACs are high quality, 24-bit Σ-Δ converters that

operate at selectable 64× or 128× oversampling ratios. The base

sampling rate of the converters is set by the input clock rate and

can be further scaled with the converter control register settings.

The converters can operate at sampling frequencies from 8 kHz

to 96 kHz. The ADCs and DACs also include very fine-step digital

volume controls.

The playback path allows input signals and DAC outputs to be

mixed into various output configurations. Headphone drivers are

available for a stereo headphone output, and the other output pins

are capable of differentially driving an earpiece speaker. Capless

headphone outputs are possible with the use of the mono output

as a virtual ground connection. The stereo line outputs can be used

as either single-ended or differential outputs and as an optional

mix-down mono output.

The DSP core introduces many features that make this codec

unique and optimized for audio processing. The program and pa-

rameter RAMs can be loaded with custom audio processing signal

flow built using the SigmaStudio graphical programming software

from Analog Devices, Inc. The values stored in the parameter RAM

control individual signal processing blocks, such as equalization

filters, dynamics processors, audio delays, and mixer levels.

The SigmaStudio software is used to program and control the Sig-

maDSP through the control port. Along with designing and tuning

a signal flow, the tools can be used to configure all of the DSP

registers. The SigmaStudio graphical interface allows anyone with

digital or analog audio processing knowledge to easily design DSP

signal flow and port it to a target application. At the same time, it

provides enough flexibility and programmability for an experienced

DSP programmer to have in-depth control of the design. In SigmaS-

tudio, the user can connect graphical blocks (such as biquad filters,

dynamics processors, mixers, and delays), compile the design, and

load the program and parameter files into the ADAU1761 memory

through the control port. Signal processing blocks available in the

provided libraries include the following:

►

Enhanced stereo capture

►

Single- and double-precision biquad filters

►

FIR filters

►

Dynamics processors with peak or rms detection for mono and

multichannel dynamics

►

Mixers and splitters

►

Tone and noise generators

►

Fixed and variable gain

►

Loudness

►

Delay

►

Stereo enhancement

►

Dynamic bass boost

►

Noise and tone sources

►

Level detectors

Additional processing blocks are always being developed. Analog

Devices also provides proprietary and third-party algorithms for

applications such as matrix decoding, bass enhancement, and

surround virtualizers. Contact Analog Devices (www.analog.com)

for information about licensing these algorithms.

The ADAU1761 can generate its internal clocks from a wide range

of input clocks by using the on-board fractional PLL. The PLL

accepts inputs from 8 MHz to 27 MHz.

The ADAU1761 is provided in a small, 32-lead, 5 mm × 5 mm

LFCSP with an exposed bottom pad.

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