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ADAU1761BCPZ-R7 数据表(PDF) 80 Page - Analog Devices

部件名 ADAU1761BCPZ-R7
功能描述  SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  92 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU1761BCPZ-R7 数据表(HTML) 80 Page - Analog Devices

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Data Sheet
ADAU1761
CONTROL REGISTERS
analog.com
Rev. F | 80 of 92
Table 134. Serial Output Route Control Register (Continued)
Bits
Bit Name
Description
1100
Reserved
1101
ADCs [L, R] to serial output [R2, L2]
1110
Reserved
1111
ADCs [L, R] to serial output [R3, L3]
R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4)
The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, these
pins are configured as GPIO interfaces to the SigmaDSP. If these bits are set to 0, they are configured as serial data I/O port pins.
Table 135.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
LRGP3
BGP2
SDOGP1
SDIGP0
Table 136. Table SEQ Table \* ARABIC 85 . Serial Data/GPIO Pin Configuration Register
Bits
Bit Name
Description
3
LRGP3
LRCLK or GPIO3 pin configuration select.
0 = LRCLK enabled (default).
1 = GPIO3 enabled.
2
BGP2
BCLK or GPIO2 pin configuration select.
0 = BCLK enabled (default).
1 = GPIO2 enabled.
1
SDOGP1
ADC_SDATA or GPIO1 pin configuration select.
0 = ADC_SDATA enabled (default).
1 = GPIO1 enabled.
0
SDIGP0
DAC_SDATA or GPIO0 pin configuration select.
0 = DAC_SDATA enabled (default).
1 = GPIO0 enabled.
R61: DSP Enable, 16,629 (0x40F5)
Table 137.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DSPEN
Table 138. DSP Enable Register
Bits
Bit Name
Description
0
DSPEN
Enables the DSP. Set this bit before writing to the parameter RAM and before setting the DSPRUN bit in Register R62 (Address 0x40F6).
0 = DSP disabled (default).
1 = DSP enabled.
R62: DSP Run, 16,630 (0x40F6)
Table 139.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DSPRUN



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