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Data Sheet

ADL5205

Rev. A | Page 17 of 31

THEORY OF OPERATION

BASIC STRUCTURE

The ADL5205 is a dual differential, digitally controlled variable

gain amplifier (DGA). Each DGA consists of a 100 Ω differential

input, digitally controlled passive attenuator followed by a

digitally controlled gain amplifier. The input, digitally controlled,

binary weighted attenuator has a range of 0 dB to 23 dB with 1 dB

steps, and the amplifier has a range of 14 dB to 26 dB, also with

1 dB steps. On-chip logic circuitry maps the gain codes such

that the first 12 dB of gain reduction from the maximum gain

are accomplished using the digitally controlled gain amplifier,

only. This topology allows the first 12 dB of gain reduction to be

accompanied by typically 1.2 dB of total noise figure degradation

(at 200 MHz). The OIP3 also remains nearly constant over the

first 12 dB of gain range. The noise figure for the DGA

increases by 1 dB for each decibel of attenuation within the

remaining 23 dB attenuation range. The differential output

impedance of the amplifier is 10 Ω.

CONTROL/LOGIC CIRCUITRY

The ADL5205 features three different gain control interfaces: serial,

parallel, or up/down control, determined by the combination of

the MODE1 and MODE0 pins. For details on controlling the

gain in each of these modes, see the Digital Interface Overview

section. In general, the gain step size is 1 dB; however, larger

step sizes can be programmed as described in the Digital

Interface Overview section. Each amplifier has a maximum gain

of +26 dB (Gain Code 000000) to −9 dB (Gain Code 100011 to

Gain Code 111111). Using the performance mode (PM) pin, users

can lower the power consumption of the device with a slight

degradation in linearity performance.

COMMON-MODE VOLTAGE

The ADL5205 is flexible in terms of input/output coupling. It

can be ac-coupled or dc-coupled at the inputs and/or outputs

within the specified output common-mode levels of 1.2 V to

2.7 V, depending on the supply voltage. If no external output

common-mode voltage is applied, the input and output common-

mode voltages are set internally to half of the supply voltage.

The output common-mode voltages of the ADL5205 are controlled

by the voltages on the VCMA and VCMB pins. Each of these pins

is connected internally through 5 kΩ resistors to the VPOS pin

as well as to the exposed pad (EP). As a result, the common-

mode output voltage at each channel is preset internally to half

of the supply voltage at VPOS. Alternatively, the VCMA and

VCMB pins can be connected to the common-mode voltage

reference output from an ADC, and thus the common-mode

levels between the two devices can be matched without

requiring any external components.

Ω

100

Ω

14dB

26dB

GND

VPOS

VINA+

VINA–

SIDE A

SPI WITH FA,

PARALLEL WITH LATCH,

UP/DOWN

VOUTA–

ADL5205

VOUTA+

MODE0

MODE1

LOGIC

CONTROL

CIRCUITRY

PWUPA

CHANNEL A

CIRCUITRY DUPLICATED FOR CHANNEL B

0dB TO 23dB

Figure 50. Basic Structure

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