ADL5205ACPZ-R7 datasheet(19/31 Pages) AD

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Data Sheet

ADL5205

Rev. A | Page 19 of 31

DIGITAL INTERFACE OVERVIEW

The three digital control interface options of the ADL5205

DGA are, respectively,

•

Parallel control interface

•

Serial peripheral interface

•

Gain step up/down interface

The digital control interface selection is made via two digital

pins, MODE1 and MODE0, as shown in Table 6. Additionally,

there are three power mode control pins, PM, PWUPA, and

PWUPB. PM selects between the high performance and low

power modes, whereas PWUPA and PWUPB enable (power-

up) the corresponding channel. The gain in each channel is

controlled by a 6-bit binary code (A5 to A0 and B5 to B0).

The same physical pins are shared between three interfaces,

resulting in as many as three different functions per digital pin (see

Table 5).

Table 6. Digital Control Interface Selection Truth Table

MODE1

MODE0

Interface

Parallel

Serial (SPI)

Up/down

Parallel Digital Interface

The parallel digital interface uses six gain control bits and a

latch pin per amplifier. The latch pin controls whether the input

data latch is transparent (logic low) or latched (logic high). In

transparent mode, the gain changes as the input gain control bits

change. In latched mode, the gain is determined by the latched

gain setting and is not changed by changing the input gain

control bits.

Serial Peripheral Interface (SPI)

The SPI uses three pins (SDIO, SCLK, and CSA or CSB). The

SPI data register consists of two bytes: six gain control bits (D0

to D5), two attenuation step size address bits (FA0 and FA1),

one read/write bit (R/W), and seven don't care bits (X), as

shown in Figure 53.

The SPI uses a bidirectional pin (SDIO) for writing to the SPI

to shift the 16 bits into the corresponding SPI register, MSB first.

Individual channel SPI registers can be selected by pulling CSA

or CSB low. By simultaneously pulling the CSA and CSB pins

low, the same data can be written to both SPI registers.

SPI register read back operation is described in the SPI Read

section. Because there is only one SDIO line, the control register

of each channel must be read back individually.

SPI fast attack mode is controlled by the FA_A or FA_B pins. A

logic high on the FA_A pin or FA_B pin results in an attenuation

selected by the FA1 and the FA0 bits in the SPI register.

Table 7. SPI 2-Bit Attenuation Step Size Truth Table

FA1

FA0

Step Size (dB)

Up/Down Interface

The up/down interface uses two digital pins to control the gain.

When the UPDN_DAT_x pin is low, the gain for the

corresponding channel is increased by a clock pulse on the

UPDN_CLK_x pin (rising and falling edges). When the

UPDN_DAT_x pin is high, the corresponding gain is decreased

by a clock pulse on the UPDN_CLK_x pin. Reset is detected

when the rising edge of UPDN_CLK_x latches one polarity on

UPDN_DAT_x, and the falling edge latches the opposite

polarity. Reset results in the minimum gain code of 111111.

UPDN_DAT_x

RESET

UPDN_CLK_x

Figure 52. Up/Down Gain Control Timing

The step size is selectable by the GS1 and GS0 pins. The default

step size is 1 dB. The gain code count rails at the top and

bottom of the control range.

Table 8. Step Size Control Truth Table

GS1

GS0

Step Size (dB)

FA0

FA1

R/W

DON’T CARE (7 BITS)

READ/WRITE

FAST ATTACK ATTENUATION STEP SIZE ADDRESS

GAIN CONTROL

LSB

DATA

MSB LSB MSB

Figure 53. 16-Bit SPI Register

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