ADL5205ACPZ-R7 datasheet(23/31 Pages) AD

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Data Sheet

ADL5205

Rev. A | Page 23 of 31

The power supply jumper configurations (S1 to S3) required for

selecting the evaluation board analog supply (VCC) and digital

supply (VDD) from the external 3.3 V or 5 V power supply are

shown in Table 11. When using a 5 V supply, enable the on-board

3.3 V voltage regulator and select it using the S3 and S2 jumpers,

respectively, to provide digital supply (VDD) to the pull-up resistors

for logic signals.

Table 11. Power Supply Selection Jumpers

Jumper

Function

Supply Selection

VCC = 3.3 V

VCC = 5 V

VCC selection

3P3V

VDD selection

3P3V

VREG

VDD LDO enable

AGND

SIGNAL INPUTS AND OUTPUTS

Signal inputs and outputs for each channel come through a pair

of SMA connectors. In the default configuration, on-board

baluns convert single-ended signals from VINA− and VINB−

into differential signals to the device. Similarly, differential output

signals from the device are converted through the on-board baluns

into single-ended form to the VOUTA+ and VOUTB+ connectors.

MANUAL CONTROLS

Three sets of switches provide the manual control of the states

of the device. Their functions are listed in Table 12. When the

individual switch is in the up position, the signal controlled by

the switch is set to logic high.

Table 12. Switch Block Functions

Switch Block

Function

Device

Pin No.

SW1

Channel B control (eight positions)

Position 1

PWUPB

Position 2

LATCHB

Position 3

Position 4

Position 5

Position 6

Position 7

Position 8

SW2

Mode control (three positions)

Position 1

Power mode (PM)

Position 2

MODE0 (M0)

Position 3

MODE1 (M1)

SW3

Channel A control (eight positions)

Position 1

Position 2

Position 3

Position 4

Position 5

Position 6

Position 7

LATCHA

Position 8

PWUPA

Mode Switches

When the power mode (PM) switch is up (logic high or Logic 1),

the device is in low power mode. When the switch is down

(logic low or Logic 0), the device is in high performance mode.

MODE1 and MODE0 (labeled M1 and M0 on the PCB) select

one of three interface modes for the device (parallel, serial/SPI,

or up/down mode), as shown in Table 13. There is no functional

difference between the mode switch settings of 10 and 11.

Table 13. Mode Switch Settings

MODE1, MODE0

Interface

Parallel

Serial (SPI)

Up/down

Channel Control Switches

The channel control switches include PWUPA, LATCHA, and A5

to A0 for Channel A and PWUPB, LATCHB, and B5 to B0 for

Channel B.

PWUPA and PWUPB are the up positions (logic high) that turn

on their respective channels. When PM is set to logic low (high

performance mode), the total current consumption increases by

approximately 81 mA (that is, one half of the difference between

the enabled current of 175 mA and the disabled current of 14 mA)

when each channel is enabled. When the PM is set to logic high

(low power mode), the total current consumption increases by

approximately 61 mA (that is, one half of the difference between

the enabled current of 135 mA and the disabled current of 14 mA)

when each channel is enabled.

The LATCHA and LATCHB switches are used with the gain control

input bits (A5 to A0 and B5 to B0) to control the corresponding

channel voltage gain. When these switches are in the down (logic

low) position, the gain changes with the position of the gain

control switches. When these switches are in the up position,

the last gain setting is latched into the corresponding channel

of the ADL5205, and the gain stops changing.

For Bits[A5:A0] and Bits[B5:B0], the following equation

determines the voltage gain of each channel of the ADL5205:

Gain = 26 − [A5:A0] dB

where [A5:A0] is the value representing the binary string formed

by Bits[A5:A0] from 0 to 35. When this value exceeds 35, the

gain is set to minimum (−9 dB). The voltage gain for Channel B

is changed by Bits[B5:B0] in the same manner.

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