DSPIC33FJ12MC02ESS datasheet(95/284 Pages) MICROCHIP

95 / 284 page

Preliminary

DS70265B-page 93

dsPIC33FJ12MC201/202

7.0

OSCILLATOR

CONFIGURATION

The

dsPIC33FJ12MC201/202

oscillator

system

provides:

• External and internal oscillator options as clock

sources

• An on-chip Phase-Locked Loop (PLL) to scale the

internal operating frequency to the required

system clock frequency

• An internal FRC oscillator that can also be used

with the PLL, thereby allowing full-speed

operation without any external clock generation

hardware

• Clock switching between various clock sources

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• A Clock Control register (OSCCON)

• Nonvolatile Configuration bits for main oscillator

selection

A simplified diagram of the oscillator system is shown

in Figure 7-1.

FIGURE 7-1:

dsPIC33FJ12MC201/202 OSCILLATOR SYSTEM DIAGRAM

Note:

This data sheet summarizes the features

of the dsPIC33FJ12MC201/202 devices.

It is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to the

“dsPIC33F Family Reference Manual”.

Please see the Microchip web site

(www.microchip.com)

for

the

latest

dsPIC33F Family Reference Manual

chapters.

dsPIC33F

Secondary Oscillator

LPOSCEN

SOSCO

SOSCI

Timer 1

OSCI

OSCO

Primary Oscillator

XTPLL, HSPLL,

XT, HS, EC

FRCDIV<2:0>

WDT, PWRT,

FSCM

FRCDIVN

SOSC

FRCDIV16

ECPLL, FRCPLL

NOSC<2:0> FNOSC<2:0>

Reset

FRC

Oscillator

LPRC

Oscillator

DOZE<2:0>

S1/S3

FRC

LPRC

÷16

Clock Switch

Clock Fail

÷ 2

TUN<5:0>

PLL(1)

FCY

FOSC

Note 1: See Figure 7-2 for PLL details.

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