DSPIC33FJ12MC02ESS datasheet(12/284 Pages) MICROCHIP

12 / 284 page

dsPIC33FJ12MC201/202

DS70265B-page 10

Preliminary

FLTA1

PWM1L1

PWM1H1

PWM1L2

PWM1H2

PWM1L3

PWM1H3

FLTA2

PWM2L1

PWM2H1

—

PWM1 Fault A input.

PWM1 Low output 1

PWM1 High output 1

PWM1 Low output 2

PWM1 High output 2

PWM1 Low output 3

PWM1 High output 3

PWM2 Fault A input.

PWM2 Low output 1

PWM2 High output 1

PGD1/EMUD1

PGC1/EMUC1

PGD2/EMUD2

PGC2/EMUC2

PGD3/EMUD3

PGC3/EMUC3

I/O

Data I/O pin for programming/debugging communication channel 1.

Clock input pin for programming/debugging communication channel 1.

Data I/O pin for programming/debugging communication channel 2.

Clock input pin for programming/debugging communication channel 2.

Data I/O pin for programming/debugging communication channel 3.

Clock input pin for programming/debugging communication channel 3.

MCLR

I/P

Master Clear (Reset) input. This pin is an active-low Reset to the device.

AVDD

Positive supply for analog modules.

AVSS

Ground reference for analog modules.

VDD

—

Positive supply for peripheral logic and I/O pins.

VDDCORE

—

CPU logic filter capacitor connection.

VSS

—

Ground reference for logic and I/O pins.

VREF+

Analog

Analog voltage reference (high) input.

VREF-

Analog

Analog voltage reference (low) input.

TABLE 1-1:

PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Type

Buffer

Type

Description

Legend: CMOS = CMOS compatible input or output

Analog = Analog input

P=Power

ST = Schmitt Trigger input with CMOS levels

O = Output

I = Input

DSPIC33FJ12MC02ESS 数据表(PDF) 12 Page - Microchip Technology

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