FALXT972MCCA4 datasheet(64/92 Pages) INTEL

64 / 92 page

Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Table 27 lists the 100BASE-TX characteristics.

Table 28 lists the 10BASE-T characteristics.

Table 29 lists the 10BASE-T link integrity timing characteristics.

Table 27. 100BASE-TX Transceiver Characteristics

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Peak differential output voltage

0.95

–

1.05

Note 2

Signal amplitude symmetry

Vss

–

102

Note 2

Signal rise/fall time

TRF

3.0

–

5.0

Note 2

Rise/fall time symmetry

TRFS

–

0.5

Note 2

Duty cycle distortion

DCD

Offset from 16 ns pulse

width at 50% of pulse

peak

Overshoot/Undershoot

VOS

––

–

Jitter (measured differentially)

–

1.4

–

1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production

testing.

2. Measured at the line side of the transformer, line replaced by 100

Ω(+/-1%) resistor.

Table 28. 10BASE-T Transceiver Characteristics

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Transmitter

Peak differential output

voltage

VOP

2.2

2.5

2.8

With transformer, line

replaced by 100

resistor

Transition timing jitter added

by the MAU and PLS

sections

–0

After line model

specified by IEEE

802.3 for 10BASE-T

MAU

Receiver

Receive Input Impedance

ZIN

––

–

Differential Squelch

Threshold

VDS

300

420

585

–

Table 29. 10BASE-T Link Integrity Timing Characteristics

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Time Link Loss Receive

TLL

–

150

–

Link Pulse

TLP

–

Link Pulses

–

Link Min Receive Timer

TLR MIN

2–

–

Link Max Receive Timer

TLR MAX

–

150

–

Link Transmit Period

Tlt

–

Link Pulse Width

Tlpw

–

150

–

1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production

testing.

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