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FALXT972MCCA4 数据表(PDF) 32 Page - Intel Corporation |
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FALXT972MCCA4 数据表(HTML) 32 Page - Intel Corporation |
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32 / 92 page  Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver 32 Datasheet Document Number: 302875-005 Revision Date: 27-Oct-2005 • During a software reset, bit settings in Table 45, “Auto-Negotiation Advertisement Register - Address 4, Hex 4” on page 79 are not re-read from the LXT972M Transceiver configuration pins. Instead, the bit settings revert to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset are not detected during a software reset. • During a software reset, registers are available for reading. To see when the LXT972M Transceiver has completed reset, the reset bit can be polled (that is, Register bit 0.15 = 0). For pin settings used during a hardware reset, see Section 5.4.4, “Hardware Configuration Settings”. During a hardware reset, configuration settings for auto-negotiation and speed are read in from pins, and register information is unavailable for 1 ms after de-assertion of the reset. |
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