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PIC16F-E/ML 数据表(PDF) 111 Page - Microchip Technology |
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PIC16F-E/ML 数据表(HTML) 111 Page - Microchip Technology |
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111 / 178 page  © 2007 Microchip Technology Inc. DS40044F-page 109 PIC16F627A/628A/648A TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS 14.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W register and Status register). This must be implemented in software. Example 14-1 stores and restores the Status and W registers. The user register, W_TEMP, must be defined in a common memory location (i.e., W_TEMP is defined at 0x70 in Bank 0 and is therefore, accessible at 0xF0, 0x170 and 0x1F0). The Example 14-1: • Stores the W register • Stores the Status register • Executes the ISR code • Restores the Status (and bank select bit register) • Restores the W register EXAMPLE 14-1: SAVING THE STATUS AND W REGISTERS IN RAM 14.7 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time out generates a device Reset. If the device is in Sleep mode, a WDT time out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as clear (Section 14.1 “Configuration Bits”). 14.7.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC Specifications, Table 17-7). If longer time- out periods are desired, a postscaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset. The TO bit in the Status register will be cleared upon a Watchdog Timer time out. 14.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time out occurs. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other Resets(1) 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation. MOVWF W_TEMP ;copy W to temp register, ;could be in any bank SWAPF STATUS,W ;swap status to be saved ;into W BCF STATUS,RP0 ;change to bank 0 ;regardless of current ;bank MOVWF STATUS_TEMP ;save status to bank 0 ;register : :(ISR) : SWAPF STATUS_TEMP,W;swap STATUS_TEMP register ;into W, sets bank to original ;state MOVWF STATUS ;move W into STATUS ;register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W |
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